1. Field of the Invention
The present invention relates to a structure of a thin film transistor and a manufacturing method thereof, and more specifically, the present invention relates to a a thin film transistor having a cystallization seed layer on an active layer, and a method of manufacturing such a thin film transistor in which an active layer is formed by crystallizing an amorphous silicon thin film.
2. Description of the Background Art
Thin film transistors (TFTs) are used as switching devices for a pixel block and as driving devices for a driver circuit block in an active matrix type liquid crystal display (LCD). It is preferable to form the TFTs of the pixel block and the driver circuit block with the same material so that the number of steps in the manufacturing process is reduced.
The TFTs of the pixel block, whether they are formed from amorphous silicon or polysilicon, do not effect the performance of the LCD. However, the TFTs in the driver circuit block require high speed performance. Thus, the TFTs of the driver circuit block should not be formed from amorphous silicon, which is characterized by low electron mobility.
Accordingly, techniques have been developed in which an active layer is made from polysilicon. In the prior art, a polysilicon film is formed by depositing amorphous silicon and then crystallizing the amorphous silicon using a heat treatment. More specifically, the amorphous silicon film is deposited at a relatively low temperature of about 350.degree. C. and then crystallized into polysilicon by a laser annealing process or other similar process. The crystallization of the amorphous silicon is performed so that silicon grains are grown from the amorphous silicon. The silicon grains stop growing as they adjoin the adjacent grains so that a grain boundary is created between the adjoining grains.
FIG. 1 is a cross-sectional view of a thin film transistor according to the prior art.
Referring to FIG. 1, a buffer layer 13 is formed on a substrate 11, and an active layer 15 made of polysilicon is formed on the buffer layer 13. A gate insulating film 19 and a gate electrode 21 made from a conductive metal such as aluminum or molybdenum is laminated on a portion of the active layer 15. For example, the gate electrode 21 is shorter than the gate insulating film 19 so that centering the gate electrode 21 with respect to the active layer 15 exposes both ends of the gate insulating film 19.
Next, N or P type impurities are implanted on each side of the gate electrode 21 within the active layer 15. Thus, the portion on the active layer 15 not covered by the gate insulating film 19 is heavily doped with impurities and forms a source region 23 and a drain region 25, while the portion that is covered by the gate insulating film 19 is lightly doped with impurities to form a lightly doped drain (LDD) region 27. The portion within the active layer 15 that is covered by the gate electrode 21 forms a channel region. Note that the active layer 15, which includes the source region 23, the drain region 25, and the LDD region 27, is made of polysilicon, which was crystallized from amorphous silicon using laser radiation.
A first insulating layer 29 made of either silicon oxide or silicon nitride is formed on the entire surface of the structure, and a first contact hole 31 exposing the source and drain regions 23 and 25 is created in the first insulating layer 29. Thereafter, the source electrode 33 and the drain electrode 34, made from a metal such as aluminum, are formed in the first contact hole 31. Thus, the source and drain electrodes 33 and 34 are electrically connected to the source and drain regions 23 and 25, respectively.
A second insulating layer 35 made from an insulator such as silicon oxide or silicon nitride is formed on the first insulating layer 29 and covers the source and drain electrodes 33 and 34. A second contact hole 37 formed in the second insulating layer 35 exposes the drain electrode 34. Thereafter, a pixel electrode 39 is formed on the second insulating layer 35. Thus, the pixel electrode 39 is electrically connected to the drain electrode 34. Note that the pixel electrode 39 is made from a transparent conductive material such as ITO (Indium Tin Oxide) or TO (Tin Oxide).
FIGS. 2A-2E are cross-sectional views illustrating a process for manufacturing a thin film transistor according to the prior art.
Referring to FIG. 2A, silicon oxide is deposited on a transparent substrate 11 such as glass using a chemical vapor deposition (CVD) method to form a buffer layer 13. Amorphous silicon is deposited on the buffer layer 13 and then crystallized with laser radiation to form an active layer 15. The buffer layer 13 prevents the impurities from the substrate 11 from penetrating into the active layer 15. Thereafter, the active layer 15 is patterned so that only a select portion thereof remains on the buffer layer 13.
Referring to FIG. 2B, an insulating material such as silicon oxide or silicon nitride is deposited using the CVD method and covers the active layer 15. Thereafter, a conductive metal such as aluminum or molybdenum is deposited on the insulating material. Next, a photoresist 17 is coated on the conductive metal and then patterned by exposure and development so that it covers the portion corresponding to the channel region of the active layer 15. Using the photoresist 17 as a mask, the conductive metal and the insulating material are then sequentially patterned to form a gate electrode 21 and a gate insulating film 19. To form the gate electrode 21, the conductive metal is patterned by an isotropic etching process which leaves the insulating material exposed. Therefter, to form the gate insulating film 19, the insulating material is etched anisotropically which leaves the active layer 15 exposed. Note that the gate electrode 21 is formed so as to be shorter than the gate insulating film 19.
Referring to FIG. 2C, the photoresist 17 is removed. Using the gate electrode 21 as a mask, an N type impurity such as phosphorus (P) or a P type impurity such as boron (B) is used to heavily dope, with low energy, the source and drain regions 23 and 25, and to lightly dope, with high energy, the LDD region 27. Note that the source and drain regions 23 and 25 are formed at an exposed portion of the active layer 15, while the LDD region 27 is formed at a select portion of the active layer 15 which is covered by the gate insulating film 19. Further, the section in the active layer 15 located below the gate electrode 21 defines a channel region in the active layer 15.
Referring to FIG. 2D, an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the structure using the CVD method to form a first insulating layer 29. Then, a select portion of the first insulating layer 29 is patterned using a photolithography process to create a first contact hole 31 that exposes the source and drain regions 23 and 25.
Next, a conductive metal such as aluminum is deposited on the first insulating layer 29 and covers the first contact hole 31 so that it comes into contact with the source and drain regions 23 and 25, thus forming a source electrode 33 and a drain electrode 34. Note that while the source and drain electrodes 33 and 34 are being created, a data line (not shown) is also formed so that it is connected to the source electrode 33.
Referring to FIG. 2E, an insulating material such as silicon oxide or silicon nitride is deposited on the first insulating layer 29 using the CVD method and covers the source and drain electrodes 33 and 34, thus forming a second insulating layer 35. Thereafter, the second insulating layer 35 is etched by a photolithography process to create a second contact hole 37 that exposes the drain electrode 34. Next, a transparent conductive material such as ITO or TO is deposited on the second insulating layer 35 and then patterned so that it is in contact with the drain electrode 34, and thus, it forms a pixel electrode 39.
As described above, the prior art thin film transistor has an active layer that is formed from amorphous silicon which is crystallized into polysilicon by a laser annealing process. However, the thin film transistor in the prior art is inadequate because the crystals that are formed during the crystallization are not uniform in size due to the non-uniform density of the laser beam used during the laser annealing process. Thus, the electrical properties of the transistor are also not uniform. Further, the bottom portion of the active layer that is not melted completely crystallizes upward and stops growing when it adjoins the adjacent grains. This causes the grain boundary to project from the surface of the active layer so that the surface of the active layer is uneven, thus further contributing to defective operation of the resulting transistor. The defective operation of the transistors causes malfunction and poor display quality on a liquid crystal display apparatus incorporating such transistors.